As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a Fin Field Effect Transistor (FinFET). FinFET devices typically include semiconductor fins with high aspect ratios and in which channel and source/drain regions are formed. A gate is formed over and along the sides of the fin structure (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices.
FinFET devices typically include semiconductor regions used to form source regions and drain regions. Metal silicides are then formed on the surfaces of the semiconductor regions in order to reduce the contact resistance between metal contact plugs (for contacting the silicide regions) and the semiconductor regions. However, with the decreasing in scaling, new challenges are presented.